1. Field of the Invention
The present invention relates to an interconnect delay fault test controller and a test apparatus using the same, and in particular, to an interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists.
2. Description of Prior Art
A board level test checks a fault in a chip mounted on a board and a fault in an interconnect wire between the chips. The test of the board gets more difficult to carry out as a design technique of the board progresses. In order to facilitate the test, an IEEE 1149.1 standard was established. A detail of the IEEE 1149.1 standard may be referenced from IEEE standard (IEEE Standard 1149.1-2001, “IEEE Standard Test Access Port and Boundary-Scan Architecture,” IEEE, June 2001).
In addition, in design of a SoC, even when the design of the SoC enables a complex system design by integrating perfectly developed cores, an integration of test between internal cores requires a lot of time and effort. In order to enable a reuse of the test as well as the design, a standard for testing the internal cores referred to as an IEEE P1500 in an aspect of a test integration has been announced. IEEE P1500 is a preliminary version of the standard for the test of the internal cores. IEEE P1500 working group proposes core test description language, a core wrapper, various TAMs (Test Access Mechanisms) in the IEEE P1500.
FIG. 1 is a timing diagram illustrating an IEEE 1149.1 boundary scan using the IEEE 1149.1 boundary scan to test a interconnect delay fault in accordance with a conventional art.
A TAP (Test Access Port) comprises a TCK (Test Clock), a TMS (Test Mode), a TDI (Test Data Input; not shown) and a TDO (Test Data Output; not shown), and may further comprise a TRST (Test Reset; not shown) port. The TCK is a clock used when the test is carried out, and the TMS is a signal for controlling a state transition of the TAP controller.
The IEEE 1149.1 specification requires two data registers including a boundary-scan register and a bypass register, and may optionally comprises a device identification register and a user-defined data register.
During a scan operation of the data register, an addressed scan register receives a data register shift enable signal ShiftDR and a data register clock signal ClockDR. In addition, a data register update signal UpdateDR updates a shadow latch.
A detailed description of the test is disclosed in the IEEE 1149.1 specification.
FIG. 1 illustrates the timing diagram of TCK, MS, ClockDR, ShiftDR and UpdateDR of the above-described signals.
The drawback of the conventional art is that a unique problem of the TAP controller wherein an update operation in an output sell and a capture operation in an input cell of the interconnect wire during the test of the interconnect delay fault using the conventional IEEE 1149.1 boundary scan takes 2.5 TCK prevents an efficient test of the interconnect delay fault.
In order to solve the problem of the conventional art, various technologies have been disclosed.
For instance, a paper by K. Lofstrom, titled “Early Capture for Boundary Scan Timing Measurements”, Proceedings of IEEE International Test Conference, pp. 417-422, 1996 discloses a method wherein an early latch is added to an input terminal of the boundary cell. That is, the TAP controller is maintained at a state of UpdateDR using the TCK and TMS, a signal EarlyCaptureClock is applied to the latch at a timing to be captured after a rising edge of the UpdateDR signal being outputted by the TAP controller. In this case, the delay fault test is possible by adjusting a time gap for applying the signal EarlyCaptureClock. However, despite the simple scheme, a method for generating the signal EarlyCaptureClock is not disclosed in detail. Moreover, a measurement of an accurate area overhead is difficult, and a design modification of the boundary cell is required when the method is employed.
A paper by J. Shin, H. Kim and S. Kang, titled “At-Speed Boundary Scan Interconnect Testing in a Board with Multiple System Clocks”, Design, Automation and Test in Europe Conf., pp. 473-477, 1999 disclose a method wherein an ECCR (Early Capture Control Register) generates the signal EarlyCaptureClock for the interconnect using different clocks by adding the ECCR to the method disclosed by Lofstrom to be able to test a board employing multiple system clock.
Contrary to Lofstrom, a paper by Y. Wu and P. Soong, titled “Interconnect Delay Fault Testing with IEEE 1149.1”, Proceedings of IEEE International Test Conference, pp. 449-457, September 1999 discloses two methods wherein a programmable delay circuit similar to the ECCR disclosed by Shin is employed instead of extending the state of UpdateDR using the TCK and the TMS. The two methods include early capturing in the UpdateDR state in the input cell and late updating in the CaptureDR state in the output cell. A ClockDR signal for the early capture signal or an UpdateDR signal for the late update are applied after a desired time gap from the programmable delay circuit. While the paper by Wu discloses a signal generating circuit and a waveform in detail, a structure is complex and the area overhead requires an optimization.
A paper by S. Park and T. Kim, titled “A New IEEE 1149.1 Boundary Scan Design for The Detection of Delay Defects”, Design, Automation and Test in Europe Conference, pp. 458-462, 2000 discloses a method wherein UpdateDR is applied trailing by 1.5 TCK by temporarily replacing the system clock with the TCK to transit a state of the TAP controller. In accordance with the method by Park, while one system clock cycle is lapsed from the UpdateDR signal to the ClockDR signal, a generation and a synchronization of a TMS pattern according to a frequency of the system clock are difficult. Accordingly, the method by Park is not completely compatible to the IEEE 1149.1.
FIG. 2 is a diagram illustrating an IEEE P1500 and a WSP (wrapper serial port) in accordance with a conventional art.
A TAM provides an electrical access of I/O port in an I/O of a system chip, denoted as TAM-In and TAM-out.
A WBC (Wrapper Boundary Cell) is a wrapper boundary cell. A detailed description of a WSI (Wrapper Serial Input), a WSO (Wrapper Serial Output), a WSC (Wrapper Serial Control) and a WIR (Wrapper Instruction Register) may be referred from related standard. The WSC includes a WRCK (wrapper clock), a WRSTN (Wrapper Reset Low), a SelectWIR, a CaptureWR, a ShiftWR and an UpdateWR.
A detailed description of the IEEE P1500 wrapper and the WSP may be referred from the related standards.
In case of the test using IEEE P1500, the update operation in the output WBC and the capture operation in the input WBC of the interconnect wiring are also delayed.